+libext+.v+.sv
+incdir+/home/ICer/gitee_path/verilog_cbb/src/async/ver_src
-y /home/ICer/gitee_path/verilog_cbb/src/async/ver_src

/home/ICer/gitee_path/verilog_cbb/src/async/ver_src/async_ver_nbit_delay.v
../top/testbench.sv